Implemented relocatable overlays (OoT runs)
This commit is contained in:
Mr-Wiseguy
parent
d2603ce07c
commit
602be9c2c6
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@ -7,6 +7,7 @@
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#include <vector>
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#include <unordered_map>
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#include <span>
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#include <unordered_set>
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#include "elfio/elfio.hpp"
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#ifdef _MSC_VER
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@ -46,13 +47,35 @@ namespace RecompPort {
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bool reimplemented;
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};
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enum class RelocType : uint8_t {
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R_MIPS_NONE = 0,
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R_MIPS_16,
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R_MIPS_32,
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R_MIPS_REL32,
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R_MIPS_26,
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R_MIPS_HI16,
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R_MIPS_LO16,
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R_MIPS_GPREL16,
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};
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struct Reloc {
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uint32_t address;
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uint32_t target_address;
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uint32_t symbol_index;
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uint32_t target_section;
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RelocType type;
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bool needs_relocation;
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};
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struct Section {
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ELFIO::Elf_Xword rom_addr;
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ELFIO::Elf64_Addr ram_addr;
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ELFIO::Elf_Xword size;
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std::vector<uint32_t> function_addrs;
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std::vector<Reloc> relocs;
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std::string name;
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bool executable;
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bool relocatable;
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};
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struct FunctionStats {
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@ -68,6 +91,8 @@ namespace RecompPort {
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std::vector<uint8_t> rom;
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// A list of the list of each function (by index in `functions`) in a given section
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std::vector<std::vector<size_t>> section_functions;
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// The section names that were specified as relocatable
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std::unordered_set<std::string> relocatable_sections;
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int executable_section_count;
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Context(const ELFIO::elfio& elf_file) {
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14
recomp.h
14
recomp.h
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@ -187,6 +187,20 @@ recomp_func_t* get_function(int32_t vram);
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#define LOOKUP_FUNC(val) \
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get_function((int32_t)(val))
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extern int32_t section_addresses[];
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#define LO16(x) \
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((x) & 0xFFFF)
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#define HI16(x) \
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(((x) >> 16) + (((x) >> 15) & 1))
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#define RELOC_HI16(section_index, offset) \
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HI16(section_addresses[section_index] + (offset))
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#define RELOC_LO16(section_index, offset) \
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LO16(section_addresses[section_index] + (offset))
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// For the Mario Party games (not working)
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//// This has to be in this file so it can be inlined
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//struct jmp_buf_storage {
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@ -17,6 +17,7 @@ typedef struct {
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uint32_t size;
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FuncEntry *funcs;
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size_t num_funcs;
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size_t index;
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} SectionTableEntry;
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#endif
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183
src/main.cpp
183
src/main.cpp
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@ -658,6 +658,8 @@ ELFIO::section* read_sections(RecompPort::Context& context, const ELFIO::elfio&
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}
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);
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std::unordered_map<std::string, ELFIO::section*> reloc_sections_by_name;
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// Iterate over every section to record rom addresses and find the symbol table
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fmt::print("Sections\n");
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for (const auto& section : elf_file.sections) {
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@ -666,10 +668,33 @@ ELFIO::section* read_sections(RecompPort::Context& context, const ELFIO::elfio&
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// Set the rom address of this section to the current accumulated ROM size
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section_out.ram_addr = section->get_address();
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section_out.size = section->get_size();
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ELFIO::Elf_Word type = section->get_type();
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std::string section_name = section->get_name();
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// Check if this section is the symbol table and record it if so
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if (type == ELFIO::SHT_SYMTAB) {
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symtab_section = section.get();
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}
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// Check if this section is a reloc section
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if (type == ELFIO::SHT_REL) {
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// If it is, determine the name of the section it relocates
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if (!section_name.starts_with(".rel")) {
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fmt::print(stderr, "Could not determine corresponding section for reloc section {}\n", section_name.c_str());
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return nullptr;
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}
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std::string reloc_target_section = section_name.substr(strlen(".rel"));
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// If this reloc section is for a section that has been marked as relocatable, record it in the reloc section lookup
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if (context.relocatable_sections.contains(reloc_target_section)) {
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reloc_sections_by_name[reloc_target_section] = section.get();
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}
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}
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// If this section isn't bss (SHT_NOBITS) and ends up in the rom (SHF_ALLOC),
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// find this section's rom address and copy it into the rom
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if (section->get_type() != ELFIO::SHT_NOBITS && section->get_flags() & ELFIO::SHF_ALLOC) {
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if (type != ELFIO::SHT_NOBITS && section->get_flags() & ELFIO::SHF_ALLOC) {
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// Find the segment this section is in to determine the physical (rom) address of the section
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auto segment_it = std::upper_bound(segments.begin(), segments.end(), section->get_offset(),
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[](ELFIO::Elf64_Off section_offset, const SegmentEntry& segment) {
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@ -677,7 +702,7 @@ ELFIO::section* read_sections(RecompPort::Context& context, const ELFIO::elfio&
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}
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);
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if (segment_it == segments.begin()) {
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fmt::print(stderr, "Could not find segment that section {} belongs to!\n", section->get_name().c_str());
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fmt::print(stderr, "Could not find segment that section {} belongs to!\n", section_name.c_str());
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return nullptr;
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}
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// Upper bound returns the iterator after the element we're looking for, so rewind by one
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@ -685,7 +710,7 @@ ELFIO::section* read_sections(RecompPort::Context& context, const ELFIO::elfio&
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const SegmentEntry& segment = *(segment_it - 1);
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// Check to be sure that the section is actually in this segment
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if (section->get_offset() >= segment.data_offset + segment.memory_size) {
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fmt::print(stderr, "Section {} out of range of segment at offset 0x{:08X}\n", section->get_name().c_str(), segment.data_offset);
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fmt::print(stderr, "Section {} out of range of segment at offset 0x{:08X}\n", section_name.c_str(), segment.data_offset);
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return nullptr;
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}
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// Calculate the rom address based on this section's offset into the segment and the segment's rom address
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@ -706,15 +731,123 @@ ELFIO::section* read_sections(RecompPort::Context& context, const ELFIO::elfio&
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section_out.executable = true;
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context.executable_section_count++;
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}
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section_out.name = section->get_name();
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section_out.name = section_name;
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}
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// Find the symbol table
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for (const auto& section : elf_file.sections) {
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// Check if this section is the symbol table and record it if so
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if (section->get_type() == ELFIO::SHT_SYMTAB) {
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symtab_section = section.get();
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if (symtab_section == nullptr) {
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fmt::print(stderr, "No symtab section found\n");
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return nullptr;
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}
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ELFIO::symbol_section_accessor symbol_accessor{ elf_file, symtab_section };
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auto num_syms = symbol_accessor.get_symbols_num();
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// TODO make sure that a reloc section was found for every section marked as relocatable
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// Process reloc sections
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for (RecompPort::Section §ion_out : context.sections) {
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// Check if a reloc section was found that corresponds with this section
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auto reloc_find = reloc_sections_by_name.find(section_out.name);
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if (reloc_find != reloc_sections_by_name.end()) {
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// Mark the section as relocatable
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section_out.relocatable = true;
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// Create an accessor for the reloc section
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ELFIO::relocation_section_accessor rel_accessor{ elf_file, reloc_find->second };
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// Allocate space for the relocs in this section
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section_out.relocs.resize(rel_accessor.get_entries_num());
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// Track whether the previous reloc was a HI16 and its previous full_immediate
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bool prev_hi = false;
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uint32_t prev_hi_immediate = 0;
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uint32_t prev_hi_symbol = std::numeric_limits<uint32_t>::max();
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for (size_t i = 0; i < section_out.relocs.size(); i++) {
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// Get the current reloc
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ELFIO::Elf64_Addr rel_offset;
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ELFIO::Elf_Word rel_symbol;
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unsigned int rel_type;
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ELFIO::Elf_Sxword bad_rel_addend; // Addends aren't encoded in the reloc, so ignore this one
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rel_accessor.get_entry(i, rel_offset, rel_symbol, rel_type, bad_rel_addend);
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RecompPort::Reloc& reloc_out = section_out.relocs[i];
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// Get the real full_immediate by extracting the immediate from the instruction
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uint32_t instr_word = byteswap(*reinterpret_cast<const uint32_t*>(context.rom.data() + section_out.rom_addr + rel_offset - section_out.ram_addr));
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rabbitizer::InstructionCpu instr{ instr_word, static_cast<uint32_t>(rel_offset) };
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//context.rom section_out.rom_addr;
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reloc_out.address = rel_offset;
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reloc_out.symbol_index = rel_symbol;
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reloc_out.type = static_cast<RecompPort::RelocType>(rel_type);
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reloc_out.needs_relocation = false;
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std::string rel_symbol_name;
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ELFIO::Elf64_Addr rel_symbol_value;
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ELFIO::Elf_Xword rel_symbol_size;
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unsigned char rel_symbol_bind;
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unsigned char rel_symbol_type;
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ELFIO::Elf_Half rel_symbol_section_index;
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unsigned char rel_symbol_other;
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bool found_rel_symbol = symbol_accessor.get_symbol(
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rel_symbol, rel_symbol_name, rel_symbol_value, rel_symbol_size, rel_symbol_bind, rel_symbol_type, rel_symbol_section_index, rel_symbol_other);
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reloc_out.target_section = rel_symbol_section_index;
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bool rel_needs_relocation = false;
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if (rel_symbol_section_index < context.sections.size()) {
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rel_needs_relocation = context.sections[rel_symbol_section_index].relocatable;
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}
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// Reloc pairing, see MIPS System V ABI documentation page 4-18 (https://refspecs.linuxfoundation.org/elf/mipsabi.pdf)
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if (reloc_out.type == RecompPort::RelocType::R_MIPS_LO16) {
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if (prev_hi) {
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if (prev_hi_symbol != rel_symbol) {
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fmt::print(stderr, "[WARN] Paired HI16 and LO16 relocations have different symbols\n"
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" LO16 reloc index {} in section {} referencing symbol {} with offset 0x{:08X}\n",
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i, section_out.name, reloc_out.symbol_index, reloc_out.address);
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}
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uint32_t rel_immediate = instr.getProcessedImmediate();
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uint32_t full_immediate = (prev_hi_immediate << 16) + (int16_t)rel_immediate;
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// Set this and the previous HI16 relocs' relocated addresses
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section_out.relocs[i - 1].target_address = full_immediate;
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reloc_out.target_address = full_immediate;
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}
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} else {
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if (prev_hi) {
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fmt::print(stderr, "Unpaired HI16 reloc index {} in section {} referencing symbol {} with offset 0x{:08X}\n",
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i - 1, section_out.name, section_out.relocs[i - 1].symbol_index, section_out.relocs[i - 1].address);
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return nullptr;
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}
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}
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if (reloc_out.type == RecompPort::RelocType::R_MIPS_HI16) {
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uint32_t rel_immediate = instr.getProcessedImmediate();
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prev_hi = true;
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prev_hi_immediate = rel_immediate;
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prev_hi_symbol = rel_symbol;
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} else {
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prev_hi = false;
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}
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if (reloc_out.type == RecompPort::RelocType::R_MIPS_32) {
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// Nothing to do here
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}
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}
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// Sort this section's relocs by address, which allows for binary searching and more efficient iteration during recompilation.
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// This is safe to do as the entire full_immediate in present in relocs due to the pairing that was done earlier, so the HI16 does not
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// need to directly preceed the matching LO16 anymore.
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std::sort(section_out.relocs.begin(), section_out.relocs.end(),
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[](const RecompPort::Reloc& a, const RecompPort::Reloc& b) {
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return a.address < b.address;
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}
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);
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}
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}
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return symtab_section;
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}
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@ -748,9 +881,22 @@ void analyze_sections(RecompPort::Context& context, const ELFIO::elfio& elf_file
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);
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}
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bool read_list_file(const char* filename, std::unordered_set<std::string>& entries_out) {
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std::ifstream input_file{ filename };
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if (!input_file.good()) {
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return false;
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}
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std::string entry;
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while (input_file >> entry) {
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entries_out.emplace(std::move(entry));
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}
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}
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int main(int argc, char** argv) {
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if (argc != 3) {
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fmt::print("Usage: {} [input elf file] [entrypoint RAM address]\n", argv[0]);
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if (argc < 3 || argc > 4) {
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fmt::print("Usage: {} [input elf file] [entrypoint RAM address] [relocatable sections list file (optional)]\n", argv[0]);
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std::exit(EXIT_SUCCESS);
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}
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@ -765,6 +911,14 @@ int main(int argc, char** argv) {
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std::exit(EXIT_FAILURE);
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};
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std::unordered_set<std::string> relocatable_sections{};
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if (argc == 4) {
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if (!read_list_file(argv[3], relocatable_sections)) {
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exit_failure("Failed to load the relocatable section list file: " + std::string(argv[3]) + "\n");
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}
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}
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std::string elf_name{ argv[1] };
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if (!elf_file.load(elf_name)) {
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@ -786,6 +940,7 @@ int main(int argc, char** argv) {
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}
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RecompPort::Context context{ elf_file };
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context.relocatable_sections = std::move(relocatable_sections);
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// Read all of the sections in the elf and look for the symbol table section
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ELFIO::section* symtab_section = read_sections(context, elf_file);
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@ -840,7 +995,7 @@ int main(int argc, char** argv) {
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"void {}(uint8_t* restrict rdram, recomp_context* restrict ctx);\n", func.name);
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//fmt::print(lookup_file,
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// " {{ 0x{:08X}u, {} }},\n", func.vram, func.name);
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if (RecompPort::recompile_function(context, func, output_dir + "ignore.txt"/*func.name + ".c"*/, static_funcs_by_section) == false) {
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if (RecompPort::recompile_function(context, func, output_dir + func.name + ".c", static_funcs_by_section) == false) {
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//lookup_file.clear();
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fmt::print(stderr, "Error recompiling {}\n", func.name);
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std::exit(EXIT_FAILURE);
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@ -957,8 +1112,8 @@ int main(int argc, char** argv) {
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std::string section_funcs_array_name = fmt::format("section_{}_{}_funcs", section_index, section_name_trimmed);
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section_load_table += fmt::format(" {{ .rom_addr = 0x{0:08X}, .ram_addr = 0x{1:08X}, .size = 0x{2:08X}, .funcs = {3}, .num_funcs = ARRLEN({3}) }},\n",
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section.rom_addr, section.ram_addr, section.size, section_funcs_array_name);
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section_load_table += fmt::format(" {{ .rom_addr = 0x{0:08X}, .ram_addr = 0x{1:08X}, .size = 0x{2:08X}, .funcs = {3}, .num_funcs = ARRLEN({3}), .index = {4} }},\n",
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section.rom_addr, section.ram_addr, section.size, section_funcs_array_name, section_index);
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fmt::print(overlay_file, "static FuncEntry {}[] = {{\n", section_funcs_array_name);
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@ -17,7 +17,8 @@ std::string_view ctx_gpr_prefix(int reg) {
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return "";
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}
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bool process_instruction(const RecompPort::Context& context, const RecompPort::Function& func, const RecompPort::FunctionStats& stats, const std::unordered_set<uint32_t>& skipped_insns, size_t instr_index, const std::vector<rabbitizer::InstructionCpu>& instructions, std::ofstream& output_file, bool indent, bool emit_link_branch, int link_branch_index, bool& needs_link_branch, bool& is_branch_likely, std::span<std::vector<uint32_t>> static_funcs_out) {
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bool process_instruction(const RecompPort::Context& context, const RecompPort::Function& func, const RecompPort::FunctionStats& stats, const std::unordered_set<uint32_t>& skipped_insns, size_t instr_index, const std::vector<rabbitizer::InstructionCpu>& instructions, std::ofstream& output_file, bool indent, bool emit_link_branch, int link_branch_index, size_t reloc_index, bool& needs_link_branch, bool& is_branch_likely, std::span<std::vector<uint32_t>> static_funcs_out) {
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const auto& section = context.sections[func.section_index];
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const auto& instr = instructions[instr_index];
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needs_link_branch = false;
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is_branch_likely = false;
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@ -37,6 +38,40 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
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return true;
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}
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bool at_reloc = false;
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bool reloc_handled = false;
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RecompPort::RelocType reloc_type = RecompPort::RelocType::R_MIPS_NONE;
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uint32_t reloc_section = 0;
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uint32_t reloc_target_section_offset = 0;
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// Check if this instruction has a reloc.
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if (section.relocatable && section.relocs[reloc_index].address == instr_vram) {
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// Get the reloc data for this instruction
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const auto& reloc = section.relocs[reloc_index];
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reloc_section = reloc.target_section;
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// Some symbols are in a nonexistent section (e.g. absolute symbols), so check that the section is valid before doing anything else.
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// Absolute symbols will never need to be relocated so it's safe to skip this.
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if (reloc_section < context.sections.size()) {
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// Check if the target section is also relocatable. References to symbols that are in a non-relocatable section don't need to
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// be relocated, so we can skip those.
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if (context.sections[reloc_section].relocatable) {
|
||||
// For games where references between sections aren't relocated, ignore this reloc if it points to a different section
|
||||
// TODO expose this as a config option
|
||||
// TODO!!!!! also relocate references to the corresponding bss section!!!!!
|
||||
if (reloc_section == func.section_index) {
|
||||
// Record the reloc's data.
|
||||
reloc_type = reloc.type;
|
||||
reloc_target_section_offset = reloc.target_address - context.sections[reloc_section].ram_addr;
|
||||
// Ignore all relocs that aren't HI16 or LO16.
|
||||
if (reloc_type == RecompPort::RelocType::R_MIPS_HI16 || reloc_type == RecompPort::RelocType::R_MIPS_LO16) {
|
||||
at_reloc = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
auto print_indent = [&]() {
|
||||
fmt::print(output_file, " ");
|
||||
};
|
||||
|
|
@ -56,7 +91,12 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
|
|||
if (instr_index < instructions.size() - 1) {
|
||||
bool dummy_needs_link_branch;
|
||||
bool dummy_is_branch_likely;
|
||||
process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, false, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely, static_funcs_out);
|
||||
size_t next_reloc_index = reloc_index;
|
||||
uint32_t next_vram = instr_vram + 4;
|
||||
if (reloc_index + 1 < section.relocs.size() && next_vram > section.relocs[reloc_index].address) {
|
||||
next_reloc_index++;
|
||||
}
|
||||
process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, false, false, link_branch_index, next_reloc_index, dummy_needs_link_branch, dummy_is_branch_likely, static_funcs_out);
|
||||
}
|
||||
print_indent();
|
||||
fmt::print(output_file, fmt_str, args...);
|
||||
|
|
@ -72,7 +112,12 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
|
|||
if (instr_index < instructions.size() - 1) {
|
||||
bool dummy_needs_link_branch;
|
||||
bool dummy_is_branch_likely;
|
||||
process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, true, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely, static_funcs_out);
|
||||
size_t next_reloc_index = reloc_index;
|
||||
uint32_t next_vram = instr_vram + 4;
|
||||
if (reloc_index + 1 < section.relocs.size() && next_vram > section.relocs[reloc_index].address) {
|
||||
next_reloc_index++;
|
||||
}
|
||||
process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, true, false, link_branch_index, next_reloc_index, dummy_needs_link_branch, dummy_is_branch_likely, static_funcs_out);
|
||||
}
|
||||
fmt::print(output_file, " ");
|
||||
fmt::print(output_file, fmt_str, args...);
|
||||
|
|
@ -98,13 +143,34 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
|
|||
|
||||
uint16_t imm = instr.Get_immediate();
|
||||
|
||||
std::string unsigned_imm_string;
|
||||
std::string signed_imm_string;
|
||||
|
||||
if (!at_reloc) {
|
||||
unsigned_imm_string = fmt::format("{:#X}", imm);
|
||||
signed_imm_string = fmt::format("{:#X}", (int16_t)imm);
|
||||
} else {
|
||||
switch (reloc_type) {
|
||||
case RecompPort::RelocType::R_MIPS_HI16:
|
||||
unsigned_imm_string = fmt::format("RELOC_HI16({}, {:#X})", reloc_section, reloc_target_section_offset);
|
||||
signed_imm_string = "(int16_t)" + unsigned_imm_string;
|
||||
reloc_handled = true;
|
||||
break;
|
||||
case RecompPort::RelocType::R_MIPS_LO16:
|
||||
unsigned_imm_string = fmt::format("RELOC_LO16({}, {:#X})", reloc_section, reloc_target_section_offset);
|
||||
signed_imm_string = "(int16_t)" + unsigned_imm_string;
|
||||
reloc_handled = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
switch (instr.getUniqueId()) {
|
||||
case InstrId::cpu_nop:
|
||||
fmt::print(output_file, "\n");
|
||||
break;
|
||||
// Arithmetic
|
||||
case InstrId::cpu_lui:
|
||||
print_line("{}{} = S32({:#X} << 16)", ctx_gpr_prefix(rt), rt, imm);
|
||||
print_line("{}{} = S32({} << 16)", ctx_gpr_prefix(rt), rt, unsigned_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_add:
|
||||
case InstrId::cpu_addu:
|
||||
|
|
@ -132,19 +198,19 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
|
|||
break;
|
||||
case InstrId::cpu_addi:
|
||||
case InstrId::cpu_addiu:
|
||||
print_line("{}{} = ADD32({}{}, {:#X})", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, (int16_t)imm);
|
||||
print_line("{}{} = ADD32({}{}, {})", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, signed_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_and:
|
||||
print_line("{}{} = {}{} & {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_andi:
|
||||
print_line("{}{} = {}{} & {:#X}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, imm);
|
||||
print_line("{}{} = {}{} & {}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, unsigned_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_or:
|
||||
print_line("{}{} = {}{} | {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_ori:
|
||||
print_line("{}{} = {}{} | {:#X}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, imm);
|
||||
print_line("{}{} = {}{} | {}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, unsigned_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_nor:
|
||||
print_line("{}{} = ~({}{} | {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
|
|
@ -153,7 +219,7 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
|
|||
print_line("{}{} = {}{} ^ {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_xori:
|
||||
print_line("{}{} = {}{} ^ {:#X}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, imm);
|
||||
print_line("{}{} = {}{} ^ {}", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, unsigned_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_sll:
|
||||
print_line("{}{} = S32({}{}) << {}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rt), rt, sa);
|
||||
|
|
@ -177,13 +243,13 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
|
|||
print_line("{}{} = SIGNED({}{}) < SIGNED({}{}) ? 1 : 0", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_slti:
|
||||
print_line("{}{} = SIGNED({}{}) < {:#X} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, (int16_t)imm);
|
||||
print_line("{}{} = SIGNED({}{}) < {} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, signed_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_sltu:
|
||||
print_line("{}{} = {}{} < {}{} ? 1 : 0", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_sltiu:
|
||||
print_line("{}{} = {}{} < {:#X} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, (int16_t)imm);
|
||||
print_line("{}{} = {}{} < {} ? 1 : 0", ctx_gpr_prefix(rt), rt, ctx_gpr_prefix(rs), rs, signed_imm_string);
|
||||
break;
|
||||
case InstrId::cpu_mult:
|
||||
print_line("result = S64({}{}) * S64({}{}); lo = S32(result >> 0); hi = S32(result >> 32)", ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
|
|
@ -207,29 +273,29 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
|
|||
// Loads
|
||||
// TODO ld
|
||||
case InstrId::cpu_lw:
|
||||
print_line("{}{} = MEM_W({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
print_line("{}{} = MEM_W({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lh:
|
||||
print_line("{}{} = MEM_H({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
print_line("{}{} = MEM_H({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lb:
|
||||
print_line("{}{} = MEM_B({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
print_line("{}{} = MEM_B({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lhu:
|
||||
print_line("{}{} = MEM_HU({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
print_line("{}{} = MEM_HU({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lbu:
|
||||
print_line("{}{} = MEM_BU({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
print_line("{}{} = MEM_BU({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
// Stores
|
||||
case InstrId::cpu_sw:
|
||||
print_line("MEM_W({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
print_line("MEM_W({}, {}{}) = {}{}", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_sh:
|
||||
print_line("MEM_H({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
print_line("MEM_H({}, {}{}) = {}{}", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_sb:
|
||||
print_line("MEM_B({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
print_line("MEM_B({}, {}{}) = {}{}", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
// TODO lwl, lwr
|
||||
// examples:
|
||||
|
|
@ -246,20 +312,20 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
|
|||
// LWR x + 2 -> 00000000 0189ABCD
|
||||
// LWR x + 3 -> FFFFFFFF 89ABCDEF
|
||||
case InstrId::cpu_lwl:
|
||||
print_line("{}{} = do_lwl(rdram, {:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
//print_line("{}{} = MEM_WL({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
print_line("{}{} = do_lwl(rdram, {}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
//print_line("{}{} = MEM_WL({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_lwr:
|
||||
//print_line("{}{} = do_lwr(rdram, {:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
//print_line("//{}{} = MEM_WR({:#X}, {}{})", ctx_gpr_prefix(rt), rt, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
//print_line("{}{} = do_lwr(rdram, {}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
//print_line("//{}{} = MEM_WR({}, {}{})", ctx_gpr_prefix(rt), rt, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
break;
|
||||
case InstrId::cpu_swl:
|
||||
print_line("do_swl(rdram, {:#X}, {}{}, {}{})", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
//print_line("MEM_WL({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
print_line("do_swl(rdram, {}, {}{}, {}{})", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
//print_line("MEM_WL({}, {}{}) = {}{}", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_swr:
|
||||
//print_line("do_swr(rdram, {:#X}, {}{}, {}{})", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
//print_line("//MEM_WR({:#X}, {}{}) = {}{}", (int16_t)imm, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
//print_line("do_swr(rdram, {}, {}{}, {}{})", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
//print_line("//MEM_WR({}, {}{}) = {}{}", signed_imm_string, ctx_gpr_prefix(base), base, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
|
||||
// Branches
|
||||
|
|
@ -356,7 +422,12 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
|
|||
if (jtbl_find_result != stats.jump_tables.end()) {
|
||||
const RecompPort::JumpTable& cur_jtbl = *jtbl_find_result;
|
||||
bool dummy_needs_link_branch, dummy_is_branch_likely;
|
||||
process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, false, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely, static_funcs_out);
|
||||
size_t next_reloc_index = reloc_index;
|
||||
uint32_t next_vram = instr_vram + 4;
|
||||
if (reloc_index + 1 < section.relocs.size() && next_vram > section.relocs[reloc_index].address) {
|
||||
next_reloc_index++;
|
||||
}
|
||||
process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, false, false, link_branch_index, next_reloc_index, dummy_needs_link_branch, dummy_is_branch_likely, static_funcs_out);
|
||||
print_indent();
|
||||
fmt::print(output_file, "switch (jr_addend_{:08X} >> 2) {{\n", cur_jtbl.jr_vram);
|
||||
for (size_t entry_index = 0; entry_index < cur_jtbl.entries.size(); entry_index++) {
|
||||
|
|
@ -471,16 +542,16 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
|
|||
case InstrId::cpu_lwc1:
|
||||
if ((ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("ctx->f{}.u32l = MEM_W({:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
print_line("ctx->f{}.u32l = MEM_W({}, {}{})", ft, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
print_line("NAN_CHECK(ctx->f{}.fl)", ft);
|
||||
} else {
|
||||
// odd fpr
|
||||
print_line("ctx->f{}.u32h = MEM_W({:#X}, {}{})", ft - 1, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
print_line("ctx->f{}.u32h = MEM_W({}, {}{})", ft - 1, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_ldc1:
|
||||
if ((ft & 1) == 0) {
|
||||
print_line("ctx->f{}.u64 = LD({:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
print_line("ctx->f{}.u64 = LD({}, {}{})", ft, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
print_line("NAN_CHECK(ctx->f{}.d)", ft);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for ldc1: f{}\n", ft);
|
||||
|
|
@ -490,15 +561,15 @@ bool process_instruction(const RecompPort::Context& context, const RecompPort::F
|
|||
case InstrId::cpu_swc1:
|
||||
if ((ft & 1) == 0) {
|
||||
// even fpr
|
||||
print_line("MEM_W({:#X}, {}{}) = ctx->f{}.u32l", (int16_t)imm, ctx_gpr_prefix(base), base, ft);
|
||||
print_line("MEM_W({}, {}{}) = ctx->f{}.u32l", signed_imm_string, ctx_gpr_prefix(base), base, ft);
|
||||
} else {
|
||||
// odd fpr
|
||||
print_line("MEM_W({:#X}, {}{}) = ctx->f{}.u32h", (int16_t)imm, ctx_gpr_prefix(base), base, ft - 1);
|
||||
print_line("MEM_W({}, {}{}) = ctx->f{}.u32h", signed_imm_string, ctx_gpr_prefix(base), base, ft - 1);
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_sdc1:
|
||||
if ((ft & 1) == 0) {
|
||||
print_line("SD(ctx->f{}.u64, {:#X}, {}{})", ft, (int16_t)imm, ctx_gpr_prefix(base), base);
|
||||
print_line("SD(ctx->f{}.u64, {}, {}{})", ft, signed_imm_string, ctx_gpr_prefix(base), base);
|
||||
} else {
|
||||
fmt::print(stderr, "Invalid operand for sdc1: f{}\n", ft);
|
||||
return false;
|
||||
|
|
@ -955,6 +1026,9 @@ bool RecompPort::recompile_function(const RecompPort::Context& context, const Re
|
|||
int num_likely_branches = 0;
|
||||
bool needs_link_branch = false;
|
||||
bool in_likely_delay_slot = false;
|
||||
const auto& section = context.sections[func.section_index];
|
||||
bool needs_reloc = section.relocatable;
|
||||
size_t reloc_index = 0;
|
||||
for (size_t instr_index = 0; instr_index < instructions.size(); ++instr_index) {
|
||||
bool had_link_branch = needs_link_branch;
|
||||
bool is_branch_likely = false;
|
||||
|
|
@ -967,8 +1041,16 @@ bool RecompPort::recompile_function(const RecompPort::Context& context, const Re
|
|||
fmt::print(output_file, "L_{:08X}:\n", *cur_label);
|
||||
++cur_label;
|
||||
}
|
||||
|
||||
// If this is a relocatable section, advance the reloc index until we reach the last one or until we get to/pass the current instruction
|
||||
if (needs_reloc) {
|
||||
while (reloc_index < (section.relocs.size() - 1) && section.relocs[reloc_index].address < vram) {
|
||||
reloc_index++;
|
||||
}
|
||||
}
|
||||
|
||||
// Process the current instruction and check for errors
|
||||
if (process_instruction(context, func, stats, skipped_insns, instr_index, instructions, output_file, false, needs_link_branch, num_link_branches, needs_link_branch, is_branch_likely, static_funcs_out) == false) {
|
||||
if (process_instruction(context, func, stats, skipped_insns, instr_index, instructions, output_file, false, needs_link_branch, num_link_branches, reloc_index, needs_link_branch, is_branch_likely, static_funcs_out) == false) {
|
||||
fmt::print(stderr, "Error in recompilation, clearing {}\n", output_path);
|
||||
output_file.clear();
|
||||
return false;
|
||||
|
|
|
|||
|
|
@ -168,7 +168,6 @@
|
|||
<ClInclude Include="..\..\recomp.h" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClCompile Include="test.cpp" />
|
||||
<_WildCardClCompile Include="..\funcs\*.c" />
|
||||
<ClCompile Include="@(_WildCardClCompile)" />
|
||||
</ItemGroup>
|
||||
|
|
|
|||
|
|
@ -15,9 +15,6 @@
|
|||
</Filter>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClCompile Include="test.cpp">
|
||||
<Filter>Source Files</Filter>
|
||||
</ClCompile>
|
||||
<ClCompile Include="@(_WildCardClCompile)" />
|
||||
<ClCompile Include="@(_WildCardClCompile)" />
|
||||
<ClCompile Include="@(_WildCardClCompile)" />
|
||||
|
|
|
|||
|
|
@ -27,6 +27,12 @@ void load_overlay(size_t section_table_index, int32_t ram) {
|
|||
func_map[ram + func.offset] = func.func;
|
||||
}
|
||||
loaded_sections.emplace_back(ram, section_table_index);
|
||||
section_addresses[section.index] = ram;
|
||||
}
|
||||
|
||||
|
||||
extern "C" {
|
||||
int32_t section_addresses[num_sections];
|
||||
}
|
||||
|
||||
extern "C" void load_overlays(uint32_t rom, int32_t ram_addr, uint32_t size) {
|
||||
|
|
@ -69,6 +75,8 @@ extern "C" void unload_overlays(int32_t ram_addr, uint32_t size) {
|
|||
uint32_t func_address = func.offset + it->loaded_ram_addr;
|
||||
func_map.erase(func_address);
|
||||
}
|
||||
// Reset the section's address in the address table
|
||||
section_addresses[section.index] = 0;
|
||||
// Remove the section from the loaded section map
|
||||
it = loaded_sections.erase(it);
|
||||
// Skip incrementing the iterator
|
||||
|
|
@ -79,6 +87,10 @@ extern "C" void unload_overlays(int32_t ram_addr, uint32_t size) {
|
|||
}
|
||||
|
||||
void init_overlays() {
|
||||
for (size_t section_index = 0; section_index < num_sections; section_index++) {
|
||||
section_addresses[section_index] = section_table[section_index].ram_addr;
|
||||
}
|
||||
|
||||
// Sort the executable sections by rom address
|
||||
std::sort(§ion_table[0], §ion_table[num_sections],
|
||||
[](const SectionTableEntry& a, const SectionTableEntry& b) {
|
||||
|
|
|
|||
Loading…
Reference in a new issue