Implemented register state tracking to identify jump tables for jr instructions
This commit is contained in:
Mr-Wiseguy
parent
84fd433dcc
commit
2300a4b6c9
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@ -137,6 +137,7 @@
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</ProjectReference>
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</ItemGroup>
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<ItemGroup>
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<ClCompile Include="src\analysis.cpp" />
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<ClCompile Include="src\main.cpp" />
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<ClCompile Include="src\recompilation.cpp" />
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</ItemGroup>
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@ -21,6 +21,9 @@
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<ClCompile Include="src\recompilation.cpp">
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<Filter>Source Files</Filter>
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</ClCompile>
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<ClCompile Include="src\analysis.cpp">
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<Filter>Source Files</Filter>
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</ClCompile>
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</ItemGroup>
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<ItemGroup>
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<ClInclude Include="lib\ELFIO\elfio\elfio.hpp">
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@ -19,6 +19,15 @@ constexpr uint32_t byteswap(uint32_t val) {
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namespace RecompPort {
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struct JumpTable {
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uint32_t vram;
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uint32_t addend_reg;
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uint32_t rom;
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uint32_t lw_vram;
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uint32_t jr_vram;
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std::vector<uint32_t> entries;
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};
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struct Function {
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uint32_t vram;
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uint32_t rom;
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@ -26,11 +35,17 @@ namespace RecompPort {
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std::string name;
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};
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struct FunctionStats {
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std::vector<JumpTable> jump_tables;
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};
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struct Context {
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std::vector<RecompPort::Function> functions;
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std::unordered_map<uint32_t, std::vector<size_t>> functions_by_vram;
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std::vector<uint8_t> rom;
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};
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bool analyze_function(const Context& context, const Function& function, const std::vector<rabbitizer::InstructionCpu>& instructions, FunctionStats& stats);
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bool recompile_function(const Context& context, const Function& func, std::string_view output_path);
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}
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2
recomp.h
2
recomp.h
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@ -104,4 +104,6 @@ typedef struct {
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uint64_t hi, lo;
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} recomp_context;
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void switch_error(const char* func, uint32_t vram, uint32_t jtbl);
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#endif
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229
src/analysis.cpp
Normal file
229
src/analysis.cpp
Normal file
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@ -0,0 +1,229 @@
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#include <set>
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#include <algorithm>
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#include "rabbitizer.hpp"
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#include "fmt/format.h"
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#include "recomp_port.h"
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extern "C" const char* RabbitizerRegister_getNameGpr(uint8_t regValue);
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// If 64-bit addressing is ever implemented, these will need to be changed to 64-bit values
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struct RegState {
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// For tracking a register that will be used to load from RAM
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uint32_t prev_lui;
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uint32_t prev_addiu;
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uint8_t prev_addend_reg;
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bool valid_lui;
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bool valid_addiu;
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bool valid_addend;
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// For tracking a register that has been loaded from RAM
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uint32_t loaded_lw_addr;
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uint32_t loaded_addr;
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uint8_t loaded_addend_reg;
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bool valid_loaded;
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RegState() = default;
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void invalidate() {
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prev_lui = 0;
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prev_addiu = 0;
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prev_addend_reg = 0;
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valid_lui = false;
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valid_addiu = false;
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valid_addend = false;
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loaded_lw_addr = 0;
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loaded_addr = 0;
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loaded_addend_reg = 0;
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valid_loaded = false;
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}
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};
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using InstrId = rabbitizer::InstrId::UniqueId;
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bool analyze_instruction(const rabbitizer::InstructionCpu& instr, const RecompPort::Function& func, RecompPort::FunctionStats& stats,
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RegState reg_states[32]) {
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// Temporary register state for tracking the register being operated on
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RegState temp{};
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int rd = (int)instr.GetO32_rd();
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int rs = (int)instr.GetO32_rs();
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int base = rs;
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int rt = (int)instr.GetO32_rt();
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int sa = (int)instr.Get_sa();
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uint16_t imm = instr.Get_immediate();
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auto check_move = [&]() {
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if (rs == 0) {
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// rs is zero so copy rt to rd
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reg_states[rd] = reg_states[rt];
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} else if (rt == 0) {
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// rt is zero so copy rs to rd
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reg_states[rd] = reg_states[rs];
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} else {
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// Not a move, invalidate rd
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reg_states[rd].invalidate();
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}
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};
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switch (instr.getUniqueId()) {
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case InstrId::cpu_lui:
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// rt has been completely overwritten, so invalidate it
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reg_states[rt].invalidate();
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reg_states[rt].prev_lui = (int16_t)imm << 16;
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reg_states[rt].valid_lui = true;
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break;
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case InstrId::cpu_addiu:
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// The target reg is a copy of the source reg plus an immediate, so copy the source reg's state
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reg_states[rt] = reg_states[rs];
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// Set the addiu state if and only if there hasn't been an addiu already
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if (!reg_states[rt].valid_addiu) {
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reg_states[rt].prev_addiu = (int16_t)imm;
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reg_states[rt].valid_addiu = true;
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} else {
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// Otherwise, there have been 2 or more consecutive addius so invalidate the whole register
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reg_states[rt].invalidate();
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}
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break;
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case InstrId::cpu_addu:
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// rd has been completely overwritten, so invalidate it
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temp.invalidate();
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// Exactly one of the two addend register states should have a valid lui at this time
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if (reg_states[rs].valid_lui != reg_states[rt].valid_lui) {
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// Track which of the two registers has the valid lui state and which is the addend
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int valid_lui_reg = reg_states[rs].valid_lui ? rs : rt;
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int addend_reg = reg_states[rs].valid_lui ? rt : rs;
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// Copy the lui reg's state into the destination reg, then set the destination reg's addend to the other operand
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temp = reg_states[valid_lui_reg];
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temp.valid_addend = true;
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temp.prev_addend_reg = addend_reg;
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} else {
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// Check if this is a move
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check_move();
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}
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reg_states[rd] = temp;
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break;
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case InstrId::cpu_daddu:
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case InstrId::cpu_or:
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check_move();
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break;
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case InstrId::cpu_lw:
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// rt has been completely overwritten, so invalidate it
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temp.invalidate();
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// If the base register has a valid lui state and a valid addend before this, then this may be a load from a jump table
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if (reg_states[base].valid_lui && reg_states[base].valid_addend) {
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// Exactly one of the lw and the base reg should have a valid lo16 value
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bool nonzero_immediate = imm != 0;
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if (nonzero_immediate != reg_states[base].valid_addiu) {
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uint32_t lo16;
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if (nonzero_immediate) {
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lo16 = (int16_t)imm;
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} else {
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lo16 = reg_states[base].prev_addiu;
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}
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uint32_t address = reg_states[base].prev_lui + lo16;
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temp.valid_loaded = true;
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temp.loaded_lw_addr = instr.getVram();
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temp.loaded_addr = address;
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temp.loaded_addend_reg = reg_states[base].prev_addend_reg;
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}
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}
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reg_states[rt] = temp;
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break;
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case InstrId::cpu_jr:
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// Ignore jr $ra
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if (rs == (int)rabbitizer::Registers::Cpu::GprO32::GPR_O32_ra) {
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break;
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}
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// Check if the source reg has a valid loaded state and if so record that as a jump table
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if (reg_states[rs].valid_loaded) {
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stats.jump_tables.emplace_back(
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reg_states[rs].loaded_addr,
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reg_states[rs].loaded_addend_reg,
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0,
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reg_states[rs].loaded_lw_addr,
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instr.getVram(),
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std::vector<uint32_t>{}
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);
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} else {
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// Inconclusive analysis
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fmt::print(stderr, "Failed to to find jump table for `jr {}` at 0x{:08X} in {}\n", RabbitizerRegister_getNameGpr(rs), instr.getVram(), func.name);
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return false;
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}
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break;
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default:
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if (instr.modifiesRd()) {
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reg_states[rd].invalidate();
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}
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if (instr.modifiesRt()) {
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reg_states[rt].invalidate();
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}
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break;
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}
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return true;
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}
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bool RecompPort::analyze_function(const RecompPort::Context& context, const RecompPort::Function& func,
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const std::vector<rabbitizer::InstructionCpu>& instructions, RecompPort::FunctionStats& stats) {
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// Create a state to track each register (r0 won't be used)
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RegState reg_states[32] {};
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// Look for jump tables
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// A linear search through the func won't be accurate due to not taking control flow into account, but it'll work for finding jtables
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for (const auto& instr : instructions) {
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if (!analyze_instruction(instr, func, stats, reg_states)) {
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return false;
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}
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}
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// Sort jump tables by their address
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std::sort(stats.jump_tables.begin(), stats.jump_tables.end(),
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[](const JumpTable& a, const JumpTable& b)
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{
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return a.vram < b.vram;
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});
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// Determine jump table sizes
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for (size_t i = 0; i < stats.jump_tables.size(); i++) {
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JumpTable& cur_jtbl = stats.jump_tables[i];
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uint32_t end_address = (uint32_t)-1;
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uint32_t entry_count = 0;
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uint32_t vram = cur_jtbl.vram;
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if (i < stats.jump_tables.size() - 1) {
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end_address = stats.jump_tables[i + 1].vram;
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}
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// TODO this assumes that the jump table is in the same section as the function itself
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cur_jtbl.rom = cur_jtbl.vram + func.rom - func.vram;
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while (vram < end_address) {
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// Retrieve the current entry of the jump table
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// TODO same as above
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uint32_t rom_addr = vram + func.rom - func.vram;
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uint32_t jtbl_word = byteswap(*reinterpret_cast<const uint32_t*>(&context.rom[rom_addr]));
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// Check if the entry is a valid address in the current function
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if (jtbl_word < func.vram || jtbl_word > func.vram + func.words.size_bytes()) {
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// If it's not then this is the end of the jump table
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break;
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}
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cur_jtbl.entries.push_back(jtbl_word);
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vram += 4;
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}
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if (cur_jtbl.entries.size() == 0) {
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fmt::print("Failed to determine size of jump table at 0x{:08X} for instruction at 0x{:08X}\n", cur_jtbl.vram, cur_jtbl.jr_vram);
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return false;
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}
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//fmt::print("Jtbl at 0x{:08X} (rom 0x{:08X}) with {} entries used by instr at 0x{:08X}\n", cur_jtbl.vram, cur_jtbl.rom, cur_jtbl.entries.size(), cur_jtbl.jr_vram);
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}
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return true;
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}
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36
src/main.cpp
36
src/main.cpp
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@ -221,7 +221,7 @@ std::unordered_set<std::string> ignored_funcs {
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"__osSetConfig",
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"__osGetConfig",
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"__osSetWatchLo",
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"__osGetWatchLo",
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"__osGetWatchLo"
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};
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int main(int argc, char** argv) {
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@ -254,21 +254,25 @@ int main(int argc, char** argv) {
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// Pointer to the symbol table section
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ELFIO::section* symtab_section = nullptr;
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// Size of the ROM as determined by the elf
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ELFIO::Elf_Xword rom_size = 0;
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// ROM address of each section
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std::vector<ELFIO::Elf_Xword> section_rom_addrs{};
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RecompPort::Context context{};
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section_rom_addrs.resize(elf_file.sections.size());
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context.functions.reserve(1024);
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context.rom.reserve(8 * 1024 * 1024);
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// Iterate over every section to record rom addresses and find the symbol table
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fmt::print("Sections\n");
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for (const std::unique_ptr<ELFIO::section>& section : elf_file.sections) {
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fmt::print(" {}: {} @ 0x{:08X}, 0x{:08X}\n", section->get_index(), section->get_name(), section->get_address(), rom_size);
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//fmt::print(" {}: {} @ 0x{:08X}, 0x{:08X}\n", section->get_index(), section->get_name(), section->get_address(), context.rom.size());
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// Set the rom address of this section to the current accumulated ROM size
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section_rom_addrs[section->get_index()] = rom_size;
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// If this section isn't bss (SHT_NOBITS) and ends up in the rom (SHF_ALLOC), increase the rom size by this section's size
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section_rom_addrs[section->get_index()] = context.rom.size();
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// If this section isn't bss (SHT_NOBITS) and ends up in the rom (SHF_ALLOC), copy this section into the rom
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if (section->get_type() != ELFIO::SHT_NOBITS && section->get_flags() & ELFIO::SHF_ALLOC) {
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rom_size += section->get_size();
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size_t cur_rom_size = context.rom.size();
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context.rom.resize(context.rom.size() + section->get_size());
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std::copy(section->get_data(), section->get_data() + section->get_size(), &context.rom[cur_rom_size]);
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}
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// Check if this section is the symbol table and record it if so
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if (section->get_type() == ELFIO::SHT_SYMTAB) {
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@ -278,16 +282,13 @@ int main(int argc, char** argv) {
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// If no symbol table was found then exit
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if (symtab_section == nullptr) {
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exit_failure("No symbol section found\n");
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exit_failure("No symbol table section found\n");
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}
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ELFIO::symbol_section_accessor symbols{ elf_file, symtab_section };
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fmt::print("Num symbols: {}\n", symbols.get_symbols_num());
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RecompPort::Context context{};
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context.functions.reserve(1024);
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for (int sym_index = 0; sym_index < symbols.get_symbols_num(); sym_index++) {
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std::string name;
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ELFIO::Elf64_Addr value;
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@ -303,7 +304,8 @@ int main(int argc, char** argv) {
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// Check if this symbol is a function or has no type (like a regular glabel would)
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// Symbols with no type have a dummy entry created so that their symbol can be looked up for function calls
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if (type == ELFIO::STT_FUNC || (type == ELFIO::STT_NOTYPE && section_index < section_rom_addrs.size())) {
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if (type == ELFIO::STT_FUNC || type == ELFIO::STT_NOTYPE) {
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if (section_index < section_rom_addrs.size()) {
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auto section_rom_addr = section_rom_addrs[section_index];
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auto section_offset = value - elf_file.sections[section_index]->get_address();
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const uint32_t* words = reinterpret_cast<const uint32_t*>(elf_file.sections[section_index]->get_data() + section_offset);
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@ -316,6 +318,16 @@ int main(int argc, char** argv) {
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std::span{ words, num_instructions },
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std::move(name)
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);
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} else {
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uint32_t vram = static_cast<uint32_t>(value);
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context.functions_by_vram[vram].push_back(context.functions.size());
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context.functions.emplace_back(
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vram,
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0,
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std::span<const uint32_t>{},
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std::move(name)
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);
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}
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}
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}
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@ -1,5 +1,6 @@
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#include <vector>
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#include <set>
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#include <unordered_set>
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#include "rabbitizer.hpp"
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#include "fmt/format.h"
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@ -16,7 +17,7 @@ std::string_view ctx_gpr_prefix(int reg) {
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return "";
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}
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bool process_instruction(const RecompPort::Context& context, size_t instr_index, const std::vector<rabbitizer::InstructionCpu>& instructions, std::ofstream& output_file, bool indent, bool emit_link_branch, int link_branch_index, bool& needs_link_branch, bool& is_branch_likely) {
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bool process_instruction(const RecompPort::Context& context, const RecompPort::Function& func, const RecompPort::FunctionStats& stats, const std::unordered_set<uint32_t>& skipped_insns, size_t instr_index, const std::vector<rabbitizer::InstructionCpu>& instructions, std::ofstream& output_file, bool indent, bool emit_link_branch, int link_branch_index, bool& needs_link_branch, bool& is_branch_likely) {
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const auto& instr = instructions[instr_index];
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needs_link_branch = false;
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is_branch_likely = false;
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@ -30,6 +31,10 @@ bool process_instruction(const RecompPort::Context& context, size_t instr_index,
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fmt::print(output_file, " // {}\n", instr.disassemble(0));
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}
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if (skipped_insns.contains(instr.getVram())) {
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return true;
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}
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auto print_indent = [&]() {
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fmt::print(output_file, " ");
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};
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@ -49,7 +54,7 @@ bool process_instruction(const RecompPort::Context& context, size_t instr_index,
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if (instr_index < instructions.size() - 1) {
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bool dummy_needs_link_branch;
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bool dummy_is_branch_likely;
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process_instruction(context, instr_index + 1, instructions, output_file, false, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely);
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process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, false, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely);
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}
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print_indent();
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fmt::print(output_file, fmt_str, args...);
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||||
|
|
@ -65,7 +70,7 @@ bool process_instruction(const RecompPort::Context& context, size_t instr_index,
|
|||
if (instr_index < instructions.size() - 1) {
|
||||
bool dummy_needs_link_branch;
|
||||
bool dummy_is_branch_likely;
|
||||
process_instruction(context, instr_index + 1, instructions, output_file, true, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely);
|
||||
process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, true, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely);
|
||||
}
|
||||
fmt::print(output_file, " ");
|
||||
fmt::print(output_file, fmt_str, args...);
|
||||
|
|
@ -102,6 +107,9 @@ bool process_instruction(const RecompPort::Context& context, size_t instr_index,
|
|||
case InstrId::cpu_addu:
|
||||
print_line("{}{} = ADD32({}{}, {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_daddu:
|
||||
print_line("{}{} = {}{} + {}{}", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
break;
|
||||
case InstrId::cpu_negu: // pseudo instruction for subu x, 0, y
|
||||
case InstrId::cpu_subu:
|
||||
print_line("{}{} = SUB32({}{}, {}{})", ctx_gpr_prefix(rd), rd, ctx_gpr_prefix(rs), rs, ctx_gpr_prefix(rt), rt);
|
||||
|
|
@ -260,6 +268,13 @@ bool process_instruction(const RecompPort::Context& context, size_t instr_index,
|
|||
nonzero_func_index = cur_func_index;
|
||||
}
|
||||
}
|
||||
if (nonzero_func_index == (size_t)-1) {
|
||||
fmt::print(stderr, "[Warn] Potential jal resolution ambiguity\n");
|
||||
for (size_t cur_func_index : matching_funcs_vec) {
|
||||
fmt::print(stderr, " {}\n", context.functions[cur_func_index].name);
|
||||
}
|
||||
nonzero_func_index = 0;
|
||||
}
|
||||
real_func_index = nonzero_func_index;
|
||||
ambiguous = false;
|
||||
} else {
|
||||
|
|
@ -295,7 +310,28 @@ bool process_instruction(const RecompPort::Context& context, size_t instr_index,
|
|||
if (rs == (int)rabbitizer::Registers::Cpu::GprO32::GPR_O32_ra) {
|
||||
print_unconditional_branch("return");
|
||||
} else {
|
||||
// TODO jump table handling
|
||||
uint32_t instr_vram = instr.getVram();
|
||||
auto find_result = std::find_if(stats.jump_tables.begin(), stats.jump_tables.end(),
|
||||
[instr_vram](const RecompPort::JumpTable& jtbl) {
|
||||
return jtbl.jr_vram == instr_vram;
|
||||
});
|
||||
if (find_result == stats.jump_tables.end()) {
|
||||
fmt::print(stderr, "No jump table found for jr at 0x{:08X}\n", instr_vram);
|
||||
}
|
||||
const RecompPort::JumpTable& cur_jtbl = *find_result;
|
||||
bool dummy_needs_link_branch, dummy_is_branch_likely;
|
||||
process_instruction(context, func, stats, skipped_insns, instr_index + 1, instructions, output_file, false, false, link_branch_index, dummy_needs_link_branch, dummy_is_branch_likely);
|
||||
print_indent();
|
||||
// TODO this will fail if the register holding the addend is mangled, add logic to emit a temp with the addend into the code
|
||||
fmt::print(output_file, "switch ({}{} >> 2) {{\n", ctx_gpr_prefix(cur_jtbl.addend_reg), cur_jtbl.addend_reg, cur_jtbl.vram);
|
||||
for (size_t entry_index = 0; entry_index < cur_jtbl.entries.size(); entry_index++) {
|
||||
print_indent();
|
||||
print_line("case {}: goto L_{:08X}; break", entry_index, cur_jtbl.entries[entry_index]);
|
||||
}
|
||||
print_indent();
|
||||
print_line("default: switch_error(__func__, 0x{:08X}, 0x{:08X})", instr_vram, cur_jtbl.vram);
|
||||
print_indent();
|
||||
fmt::print(output_file, "}}\n");
|
||||
}
|
||||
break;
|
||||
case InstrId::cpu_bnel:
|
||||
|
|
@ -685,7 +721,7 @@ bool process_instruction(const RecompPort::Context& context, size_t instr_index,
|
|||
}
|
||||
|
||||
bool RecompPort::recompile_function(const RecompPort::Context& context, const RecompPort::Function& func, std::string_view output_path) {
|
||||
fmt::print("Recompiling {}\n", func.name);
|
||||
//fmt::print("Recompiling {}\n", func.name);
|
||||
std::vector<rabbitizer::InstructionCpu> instructions;
|
||||
|
||||
// Open the output file and write the file header
|
||||
|
|
@ -717,6 +753,24 @@ bool RecompPort::recompile_function(const RecompPort::Context& context, const Re
|
|||
vram += 4;
|
||||
}
|
||||
|
||||
// Analyze function
|
||||
RecompPort::FunctionStats stats{};
|
||||
if (!RecompPort::analyze_function(context, func, instructions, stats)) {
|
||||
fmt::print(stderr, "Failed to analyze {}\n", func.name);
|
||||
output_file.clear();
|
||||
return false;
|
||||
}
|
||||
|
||||
std::unordered_set<uint32_t> skipped_insns{};
|
||||
|
||||
// Add jump table labels into function
|
||||
for (const auto& jtbl : stats.jump_tables) {
|
||||
skipped_insns.insert(jtbl.lw_vram);
|
||||
for (uint32_t jtbl_entry : jtbl.entries) {
|
||||
branch_labels.insert(jtbl_entry);
|
||||
}
|
||||
}
|
||||
|
||||
// Second pass, emit code for each instruction and emit labels
|
||||
auto cur_label = branch_labels.cbegin();
|
||||
vram = func.vram;
|
||||
|
|
@ -737,7 +791,7 @@ bool RecompPort::recompile_function(const RecompPort::Context& context, const Re
|
|||
++cur_label;
|
||||
}
|
||||
// Process the current instruction and check for errors
|
||||
if (process_instruction(context, instr_index, instructions, output_file, false, needs_link_branch, num_link_branches, needs_link_branch, is_branch_likely) == false) {
|
||||
if (process_instruction(context, func, stats, skipped_insns, instr_index, instructions, output_file, false, needs_link_branch, num_link_branches, needs_link_branch, is_branch_likely) == false) {
|
||||
fmt::print(stderr, "Error in recompilation, clearing {}\n", output_path);
|
||||
output_file.clear();
|
||||
return false;
|
||||
|
|
|
|||
Loading…
Reference in a new issue